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cystech electronics corp. spec. no. : c778g6 issued date : 2012.02.10 revised date : 2012.10.09 page no. : 1/9 MTS3572G6 cystek product specification n- and p-channel enhancement mode power mosfet MTS3572G6 description the MTS3572G6 consists of a n-channel and a p- channel enhancement-mode mosfet in a single tsop-6 package, providing the designer with the be st combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. the tsop-6 package is universally preferred for a ll commercial-industrial surface mount applications. features ? simple drive requirement ? low gate charge ? low on-resistance ? fast switching speed ? pb-free package equivalent circuit outline MTS3572G6 tsop-6 s2 g2 d1 g gate s source d drain g1 d2 s1 pin 1
cystech electronics corp. spec. no. : c778g6 issued date : 2012.02.10 revised date : 2012.10.09 page no. : 2/9 MTS3572G6 cystek product specification absolute maximum ratings (ta=25 c) limits parameter symbol n-channel p-channel unit drain-source breakdown voltage bv dss 60 -20 v gate-source voltage v gs 20 12 v continuous drain current @t a =25 c (note 1) i d 0.3 -4.3 a continuous drain current @t a =70 c (note 1) i d 0.24 -3.4 a pulsed drain current (note 2) i dm 0.8 -20 a pd 1.14 w total power dissipation (note 1) linear derating factor 0.01 w / c operating junction and storage temperature tj, tstg -55~+150 c thermal resistance, junction-to-ambient (note 1) rth,ja 110 c/w note : 1.surface mounted on 1 in2 copper pad of fr-4 board, t 5 sec; 180 c/w when mounted on minimum copper pad 2. pulse width limited by maximum junction temperature n-channel electrical characteristics (tj=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 60 - - v v gs =0, i d =250 a v gs(th) 1.0 - 2.5 v v ds =v gs , i d =250 a i gss - - 10 v gs =20v, v ds =0 - - 1 v ds =60v, v gs =0 i dss - - 10 a v ds =48v, v gs =0, tj=70c - 1.5 2.5 i d =300ma, v gs =10v - 1.9 3 i d =100ma, v gs =4.5v *r ds(on) - 3.3 6 i d =10ma, v gs =2.5v *g fs 100 240 - ms v ds =10v, i d =100ma dynamic ciss - 30.6 - coss - 5.5 - crss - 4 - pf v ds =10v, v gs =0, f=1mhz *t d(on) - 2.6 - *t r - 7.1 - *t d(off) - 8.6 - *t f - 15 - ns v ds =30v, i d =100ma, v gs =5v, r g =25 *qg - 0.7 - *qgs - 0.3 - *qgd - 0.1 - nc v ds =30v, i d =0.3a, v gs =4.5v source-drain diode *i s - - 0.3 *i sm - - 0.8 a *v sd - - 1.2 v v gs =0v, i s =100ma *pulse test : pulse width 300 s, duty cycle 2% cystech electronics corp. spec. no. : c778g6 issued date : 2012.02.10 revised date : 2012.10.09 page no. : 3/9 MTS3572G6 cystek product specification p-channel electrical characteristics (tj=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss -20 - - v v gs =0, i d =-250 a v gs(th) -0.4 - -1 v v ds =v gs , i d =-250 a i gss - - 20 v gs =12v, v ds =0 - - -1 v ds =-20v, v gs =0 i dss - - -25 a v ds =-16v, v gs =0, tj=70 c - - 52 i d =-4a, v gs =-4.5v - - 60 i d =-4a, v gs =-2.5v *r ds(on) - - 75 m i d =-2a, v gs =-1.8v *g fs - 4 - s v ds =-10v, i d =-1a dynamic ciss - 1220 - coss - 103 - crss - 92 - pf v ds =-10v, v gs =0, f=1mhz *t d(on) - 12.5 - *t r - 12 - *t d(off) - 70 - *t f - 20 - ns v ds =-10v, i d =-1a, v gs =-4.5v, r g =6 , r d =10 *qg - 10 - *qgs - 1.9 - *qgd - 2.7 - nc v ds =-10v, i d =-4.3a, v gs =-4.5v source-drain diode *i s - - -1 *i sm - - -4 a *v sd - - -1.2 v v gs =0v, i s =-1a *pulse test : pulse width 300 s, duty cycle 2% ordering information device package shipping marking MTS3572G6 tsop-6 (pb-free lead plating package) 3000 pcs / tape & reel 3572 cystech electronics corp. spec. no. : c778g6 issued date : 2012.02.10 revised date : 2012.10.09 page no. : 4/9 MTS3572G6 cystek product specification n-channel characteristic curves typical output characteristics 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 024681012 drain-source voltage -vds(v) drain current - id(a) 3.5v 4v vgs=2v 2.5v 4.5v 6v 10v drain current vs gate-source voltage 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 012345678910 gate-source voltage-vgs(v) drain current-id(a) 125c vds=10v 25c -55c static drain-source on-state resistance vs drain current 1 10 0.001 0.01 0.1 1 drain current-id(a) static drain-source on-state resistance-rds(on)() vgs=2.5v vgs=4.5v vgs=10v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 0 0.2 0.4 0.6 0.8 1 reverse drain current -idr(a) source-drain voltage-vsd(v) tj=25c tj=150c static drain-source on-state resistance vs gate-source voltage 0 1 2 3 4 5 6 7 024681 0 drain-source on-state resistance vs junction tempearture 0 1 2 3 4 5 6 7 -60 -20 20 60 100 140 180 junction temperature-tj(c) static drain-source on-state resistance-rds(on)() vgs=10v, id=100ma gate-source voltage-vgs(v) static drain-source on-state resistance-rds(on)() id=100ma cystech electronics corp. spec. no. : c778g6 issued date : 2012.02.10 revised date : 2012.10.09 page no. : 5/9 MTS3572G6 cystek product specification n-channel characteri stic curves(cont.) capacitance vs drain-to-source voltage 1 10 100 0.1 1 10 100 drain-source voltage -vds(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.8 1 1.2 1.4 1.6 -60 -20 20 60 100 140 junction temperature-tj(c) threshold voltage-vgs(th)(v) id=250 a maximum safe operating area 0.01 0.1 1 0.01 0.1 1 10 100 v ds , drain-source voltage(v) i d , drain current (a) 10 s r ds( on) limit 100 s 1ms 10ms 100ms t a =25c, tj=150c v gs =10v single pulse dc gate charge characteristics 0 1 2 3 4 5 6 7 8 9 10 00.511.52 qg, total gate charge(nc) v gs , gate-source voltage(v) v ds =30v i d =0.3a transient thermal res 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e- t 1 , square wave r(t), normalized effectivetransient thermal resistance ponse curves 01 1.e+00 1.e+01 1.e+02 pulse duration(s) d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *r ja (t) 4.r ja =180 c/w 0.2 0.1 0.05 single pulse 0.02 0.01 cystech electronics corp. spec. no. : c778g6 issued date : 2012.02.10 revised date : 2012.10.09 page no. : 6/9 MTS3572G6 cystek product specification p-channel characteristic curves typical output characteristics 0 5 10 15 20 012345 -v ds , drain-source voltage(v) -i d , drain current (a) -v gs =1.5v -v gs =1.8v 5v 4.5 v 4v 3.5 v 3v 2.5 v brekdown voltage vs ambient temperature 20 22 24 26 28 30 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) -bv dss , drain-source breakdown voltage (v) i d =-250 a, v gs =0v static drain-source on-state resistance vs drain current 10 100 1000 0.001 0.01 0.1 1 10 -i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =-10v v gs =-1.8v v gs =-4.5v v gs =-2.5v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 024681 -i dr , reverse drain current (a) -v sd , source-drain voltage(v) 0 tj=25c tj=150c v gs =0v static drain-source on-state resistance vs gate-source voltage 0 20 40 60 80 100 120 140 160 180 200 024681 0 drain-source on-state resistance vs junction tempearture 20 30 40 50 60 70 80 90 100 -60 -20 20 60 100 140 180 tj, junction temperature(c) r ds( on) , static drain-source on-state resistance(m) v gs =-1.8v, i d =-2a v gs =-4.5v, i d =-4.3a v gs =-2.5v , i d =-2.5a -v gs , gate-source voltage(v) r ds( on) , static drain-source on- state resistance(m) i d =-4.3a i d =-2.5a i d =-0.2a cystech electronics corp. spec. no. : c778g6 issued date : 2012.02.10 revised date : 2012.10.09 page no. : 7/9 MTS3572G6 cystek product specification p-channel characteristic curves(cont.) capacitance vs drain-to-source voltage 10 100 1000 10000 0.1 1 10 100 -v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -60 -40 -20 0 20 40 60 80 100 120 140 160 tj, junction temperature(c) -v gs( th) ,threshold voltage-(v) i d =-250 a maximum safe operating area 0.01 0.1 1 10 100 0.01 0.1 1 10 100 -v ds , drain-source voltage(v) -i d , drain current (a) dc 10ms 100ms 1ms 100 s t a =25c, tj=150c v gs =-4.5v single pulse 10 s gate charge characteristics 0 2 4 6 8 10 0 2 4 6 8 101214161820 qg, total gate charge(nc) -v gs , gate-source voltage(v) v ds =-10v i d =-4.3a transient thermal response curves 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 t 1 , square wave pulse duration(s) r(t), normalized effectivetransient thermal resistance d=0.5 0.2 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *r ja (t) 4.r ja =180 c/w 0.1 0.05 single pulse 0.02 0.01 cystech electronics corp. spec. no. : c778g6 issued date : 2012.02.10 revised date : 2012.10.09 page no. : 8/9 MTS3572G6 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface. cystech electronics corp. spec. no. : c778g6 issued date : 2012.02.10 revised date : 2012.10.09 page no. : 9/9 MTS3572G6 cystek product specification tsop-6 dimension marking: 6-lead tsop-6 plastic surface mounted package cystek package code: g6 style: pin 1. gate1 (g1) pin 2. source1 (s1) pin 3. drain2 (d2) pin 4. source2 (s2) pin 5. gate2 (g2) pin 6. drain1 ( d1 ) 3572 device name date code millimeters inches millimeters inches dim min. max. min. max. dim min. max. min. max. a 0.700 0.900 0.028 0.035 e 1.600 1.700 0.063 0.067 a1 0.000 0.100 0.000 0.004 e1 2.650 2.950 0.104 0.116 a2 0.700 0.800 0.028 0.031 e 0.95 (bsc) 0.037 (bsc) b 0.350 0.500 0.014 0.020 e1 1.90 (bsc) 0.075 (bsc) c 0.080 0.200 0.003 0.008 l 0.300 0.600 0.012 0.024 d 2.820 3.020 0.111 0.119 0 8 0 8 notes : 1.controlling dimension : millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material : ? lead : pure tin plated. ? mold compound : epoxy resin family, flammability solid burning class:ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance . |
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